1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a capacitor, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, large scale integration circuits (LSIs), each of which has a plurality of MOS transistors and resistors integrated on a single chip, have been employed for main parts of computers or electric equipment.
Among LSIs, devices such as DRAMs (Dynamic Random Access Memories) have been rapidly decreased in size. DRAMs include capacitors for storing charges. A structure of a capacitor of DRAM and a method of manufacturing the capacitor are disclosed in, for example, Japanese Unexamined Patent Application, First Publication No. 2003-243534.
As disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-243534, after MISFET for memory cell selection is formed on a semiconductor substrate, a capacitor interlayer insulating film including a silicon nitride film and an insulating film is formed. A silicon oxide film is used for the insulating film of the capacitor interlayer insulating film. The silicon oxide film is formed by a plasma CVD method using ozone (O3) and tetraethoxysilane (TEOS) as reaction gases. Next, a groove (hole) is formed in the capacitor interlayer insulating film to expose a plug of the memory cell selection MISFET. For example, the groove (hole) is formed by an etching process using a photoresist film as a mask. A capacitor is formed by forming a bottom electrode film, a capacitive insulating film and a top electrode film in order in the formed groove (hole). The bottom electrode film, the capacitive insulating film and the top electrode film are mainly formed by a CVD method.
For the silicon oxide film of the capacitor interlayer insulating film, when the hole is formed by the etching process using the photoresist film as the mask, it is assumed that the section of the formed hole is tapered down. Such a shape of the hole is disclosed in, for example, “A. J. J. Huang, et al, in Proceedings of International Symposium on Dry Process 2006 (The Institute of Electrical Engineers of Japan), p. 263-264.”
However, when the bottom electrode film, the capacitive insulating film and the top electrode film are to be formed in the taper-shaped hole using the CVD method, it is difficult to supply a reaction gas throughout the inside of the hole, particularly into the bottom of the hole, which may result in difficulty in obtaining a uniform film. Specifically, there may occur a portion in which an electrode film or the like is not formed, which may result in lowering of coverage of the electrode film or the like for the inner side of the hole. In addition, there may be a high possibility of local irregularity of film thickness (partially thin film) and poor film quality, which may result in an increase of leakage current of the capacitor and failure to attain high reliability.